A generic network-on-chip architecture for reconfigurable systems:: Implementation and evaluation

The design of electronic systems in a System-on-Chip (SoC) depends on the reliable and efficient interconnection of many different components. The Network-on-Chip (NoC) is a scalable communication infrastructure able to tackle the communication needs of future SoC. However, routers of a NoC introduce a relative area overhead and increase the average latency. Therefore, in the design process it is important to consider mechanisms to improve area and performance of NoC infrastructures. In this paper, we propose a generic NoC architecture that can be tailored to the specific requirements of the system looking to improve area usage, average communication latency and throughput. An extensive analysis and tests of the proposed architecture have been performed to evaluate the approach.