A generic reconfigurable neural network architecture implemented as a network on chip

被引：19

作者：

Theocharides, T ^{[1
]}

Link, G ^{[1
]}

Vijaykrishnan, N ^{[1
]}

Irwin, MJ ^{[1
]}

Srikantam, V ^{[1
]}

机构：

[1] Penn State Univ, University Pk, PA 16802 USA

来源：

IEEE INTERNATIONAL SOC CONFERENCE, PROCEEDINGS | 2004年

关键词：

D O I：

10.1109/SOCC.2004.1362404

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Neural networks are widely used in pattern recognition, security applications and data manipulation. We propose a novel hardware architecture for a generic neural network, using Network on Chip (NoC) interconnect. The proposed architecture allows for expandability, mapping of more than one logical unit onto a single physical unit, and dynamic reconfiguration based on application-specific demands. Simulation results show that this architecture has significant performance benefits over existing architectures.

引用

页码：191 / 194

页数：4

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