A low voltage four-quadrant analog multiplier using Triode-MOSFETs

被引：0
|
作者：
Kiatwarin, N.
Sawigun, C.
Kiranon, W.
机构：
来源：
2006 International Symposium on Communications and Information Technologies,Vols 1-3 | 2006年
关键词：
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A low voltage four-quadrant analog multiplier circuit is presented. Based on triode region operation of MOSFET, the multiplier circuit can be simply realized by connecting a pair of PMOS with three flipped voltage follower circuits. As a result, the proposed circuit is compact and can be operated under low voltage supply. Circuit simulation using SPICE with 0.35 micron CMOS model parameter shows that under 1.5V single supply the proposed multiplier provides linear range of more than 50% of voltage supply (measured from THD less than 1%) and small signal bandwidth is higher than 95MHZ while the entire circuit consumes 46.4 mu W of electrical power.
引用
收藏
页码：290 / 293
页数：4
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