Low Clamping Voltage Protection for Improvements of Powered ESD Robustness

被引：0
|
作者：
Narita, Koki [1 ]
Okushima, Mototsugu [1 ]
机构：
[1] Renesas Elect Corp, 5-20-1 Josuihon Cho, Kodaira, Tokyo 1878588, Japan
来源：
2018 40TH ELECTRICAL OVERSTRESS/ELECTROSTATIC DISCHARGE SYMPOSIUM (EOS/ESD) | 2018年
关键词：
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
An on-chip protection for improvements of powered ESD robustness is presented. The proposed power clamp achieved to reduce the clamping voltage against powered ESD events compared to a conventional RC-triggered clamp by extending of the big-MOS active time with also consideration to false activation.
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页数：8
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