Impact of parasitic resistance on the ESD robustness of high-voltage devices

被引：2

作者：

Lin Lijuan ^{[1
]}

Jiang Lingli ^{[1
]}

Fan Hang ^{[1
]}

Zhang Bo ^{[1
]}

机构：

[1] Univ Elect Sci & Technol, State Key Lab Elect Thin Films & Integrated Devic, Chengdu 610054, Sichuan, Peoples R China

来源：

JOURNAL OF SEMICONDUCTORS | 2012年 / 33卷 / 01期

基金：

中国国家自然科学基金;

关键词：

electrostatic discharge; high-voltage device; LDMOS; parasitic resistance;

D O I：

10.1088/1674-4926/33/1/014005

中图分类号：

O469 [凝聚态物理学];

学科分类号：

070205 ;

摘要：

The impacts of substrate parasitic resistance and drain ballast resistance on electrostatic discharge (ESD) robustness of LDMOS are analyzed. By increasing the two parasitic resistances, the ESD robustness of LDMOS are significantly improved. The proposed structures have been successfully verified in a 0.35 mu m BCD process without using additional process steps. Experimental results show that the second breakdown current of the optimal structure increases to 3.5 A, which is about 367% of the original device.

引用

页数：5

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