Improvement on CDM ESD Robustness of High-Voltage Tolerant nLDMOS SCR Devices by Using Differential Doped Gate

被引：0

作者：

Chen, S. -H. ^{[1
]}

Linten, D. ^{[1
]}

Scholz, M. ^{[1
]}

Hellings, G. ^{[1
]}

Boschke, R. ^{[2
]}

Groeseneken, G. ^{[2
]}

Huang, Y. -C. ^{[3
]}

Ker, M. -D. ^{[3
]}

机构：

[1] IMEC, Kapeldreef 75, B-3001 Leuven, Belgium

[2] Katholieke Univ Leuven, Dept Elect Engn, B-3001 Leuven, Belgium

[3] Natl Chiao Tung Univ, Dept Elect Engn, Hsinchu, Taiwan

来源：

2014 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM | 2014年

关键词：

Electrostatic Discharge (ESD); laterally diffused nMOS (nLDMOS); high-voltage tolerant (HVT) devices; transmission line pulsing (TLP) system; very fast TLP system (VFTLP); gate oxide reliability; PART I; BEHAVIOR;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Early failure has been observed during CDM ESD stress on high-voltage tolerant nLDMOS-SCR devices in a standard low-voltage CMOS technology due to the gate oxide (GOX) degradation. In this work, we propose a special p+/n+ differential doped gate which boosts the CDM ESD failure current level with a factor of 3 to 9.

引用

页数：5

共 22 条

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