Robust and area-efficient nLDMOS-SCR with waffle layout structure for high-voltage ESD protection

被引：13
|
作者：
Zheng, J. [1 ]
Han, Y. [1 ]
Wong, H. [1 ]
Song, B. [1 ]
Dong, S. [1 ]
Ma, F. [1 ]
Zhong, L. [1 ]
机构：
[1] Zhejiang Univ, Dept ISEE, ESD Lab, Hangzhou 310027, Zhejiang, Peoples R China
来源：
ELECTRONICS LETTERS | 2012年 / 48卷 / 25期
关键词：
DEVICE;
D O I：
10.1049/el.2012.3548
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A novel waffle-type nLDMOS-SCR ESD clamp with compact source and drain for high-voltage ESD protection is proposed and realised using the 0.35 mu m, 30/5 V bipolar-CMOS-DMOS (BCD) process. With this new structure, a high ESD failure current of 4.4 A was achieved with a total channel width of only 60 mm. Considering the area efficiency, the waffle-type structure provides more than 30% higher current handling capability than the conventional ones. Because of its better robustness and area efficiency, the waffle-type structure should be a promising layout for high-voltage ESD protection applications.
引用
收藏
页码：1629 / 1630
页数：2
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