HBM and TLP ESD robustness in smart-power protection structures

被引:2
|
作者
Santirosi, S
Meneghesso, G
Novarini, E
Contiero, C
Zanoni, E
机构
[1] ST Microelect, Dedicated Prod Grp, I-20010 Milan, Italy
[2] Univ Padua, Dipartimento Elettron & Informat, I-35131 Padua, Italy
[3] IMFM, Padua, Italy
[4] Corsorzio Padova Ric, Padua, Italy
关键词
D O I
10.1016/S0026-2714(99)00110-9
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
In this paper we will present data concerning the ESD robustness of smart power protection structures (BCD technology) for input-output circuits. A comparison between the robustness of "p-body" and "p-well" based structures and a study of the influence of layout parameters on the ESD robustness will be given. The correlation between ESD robustness obtained with different test methods (HBM and TLP) will be also presented. (C) 1999 Elsevier Science Ltd. All rights reserved.
引用
收藏
页码:839 / 844
页数:6
相关论文
共 50 条
  • [1] TLP and HBM ESD Test Correlation for Power ICs
    Ma, Rui
    Wang, Li
    Zhang, Chen
    Lu, Fei
    Dong, Zongyu
    Wang, Albert
    Lu, Wei
    Song, Yonghua
    Zhao, Bin
    2013 IEEE INTERNATIONAL CONFERENCE OF ELECTRON DEVICES AND SOLID-STATE CIRCUITS (EDSSC), 2013,
  • [2] Damage analysis in smart-power technology electrostatic discharge (ESD) protection devices
    Pogany, D
    Seliger, N
    Litzenberger, M
    Gossner, H
    Stecher, M
    Müller-Lynch, T
    Werner, W
    Gornik, E
    MICROELECTRONICS RELIABILITY, 1999, 39 (6-7) : 1143 - 1148
  • [3] Different failure signatures of multiple TLP and HBM stresses in an ESD robust protection structure
    Guitard, N
    Essely, F
    Trémouilles, D
    Bafleur, M
    Nolhier, N
    Perdu, P
    Touboul, A
    Pouget, V
    Lewis, D
    MICROELECTRONICS RELIABILITY, 2005, 45 (9-11) : 1415 - 1420
  • [4] Transient interferometric mapping of smart power SOI ESD protection devices under TLP and vf-TLP stress
    Bychikhin, S
    Dubec, V
    Pogany, D
    Gornik, E
    Graf, A
    Dudek, V
    Soppa, W
    MICROELECTRONICS RELIABILITY, 2004, 44 (9-11) : 1687 - 1692
  • [5] SMART-POWER PROCESS PUTS OVERVOLTAGE PROTECTION ON CHIP
    SCHULTZ, W
    ELECTRONICS, 1984, 57 (13): : 134 - 136
  • [6] ESD protection structures for BCD5 smart power technologies
    Sponton, L
    Cerati, L
    Croce, G
    Chrappan, F
    Contiero, C
    Meneghesso, G
    Zanoni, E
    MICROELECTRONICS RELIABILITY, 2001, 41 (9-10) : 1683 - 1687
  • [7] ESD protection design for 900-MHz RF receiver with 8-kV HBM ESD robustness
    Ker, MD
    Lo, WY
    Lee, CM
    Chen, CP
    Kao, HS
    2002 IEEE RADIO FREQUENCY INTEGRATED CIRCUITS (RFIC) SYMPOSIUM, DIGEST OF PAPERS, 2002, : 427 - 430
  • [8] ESD protection design for 900-MHz RF receiver with 8-kV HBM ESD robustness
    Ker, MD
    Lo, WY
    Lee, CM
    Chen, CP
    Kao, HS
    2002 IEEE MTT-S INTERNATIONAL MICROWAVE SYMPOSIUM DIGEST, VOLS 1-3, 2002, : 537 - 540
  • [9] Investigation on ESD Robustness of 1200-V D-Mode GaN MIS-HEMTs with HBM ESD Test and TLP Measurement
    Ke, Chao-Yang
    Wang, Wei-Cheng
    Ker, Ming-Dou
    Yang, Chih-Yi
    Chang, Edward Yi
    2023 INTERNATIONAL VLSI SYMPOSIUM ON TECHNOLOGY, SYSTEMS AND APPLICATIONS, VLSI-TSA/VLSI-DAT, 2023,
  • [10] TCAD methodology for ESD robustness prediction of Smart Power ESD devices
    Salamero, Christophe
    Nolhier, Nicolas
    Gendron, Amaury
    Bafleur, Marise
    Besse, Patrice
    Zecri, Michel
    IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, 2006, 6 (03) : 399 - 407