Low Power Implementation of FM0/Manchester Encoding Using SOLS Technique

被引：0

作者：

Nikhade, Rahul N. ^{[1
]}

Charles, Priya ^{[1
]}

机构：

[1] DY Patil Coll Engn, Pune 411044, Maharashtra, India

来源：

2016 INTERNATIONAL CONFERENCE ON AUTOMATIC CONTROL AND DYNAMIC OPTIMIZATION TECHNIQUES (ICACDOT) | 2016年

关键词：

DSRC; SOLS; VLSI; FM0; code; Manchester code; hardware utilization rate (HUR);

D O I：

暂无

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

DSRC (Dedicated Short Range communication) is an emerging technique that permits very high data transmission critical in communications- based active safety applications. DSRC standards usually adopt either FM0 code or Manchester code as a coding technique to enhance signal reliability, to reach dc balance. The code word structure of FM0 and Manchester are different, thus limiting the hardware potential of existing DSRC systems. Similarity oriented logic simplification (SOLS) techniques merges hardware architectures of both FM0 and Manchester and integrated architecture gives better hardware utilization rate (HUR). The performance of this paper is validated on Xilinx ISE design suite 14.7.

引用

页码：333 / 338

页数：6

共 50 条

[41] LOW POWER SVM MODULE USING SPURIOUS POWER SUPPRESSION TECHNIQUE
Ravanya, R.
Ramya, S.
2015 2ND INTERNATIONAL CONFERENCE ON ELECTRONICS AND COMMUNICATION SYSTEMS (ICECS), 2015, : 429 - 433
[42] Low-Power Counters using Pathfinding Technique
He, Yixuan
Choi, Minsu
Kim, Kyung-Ki
Kim, Yong-Bin
2023 20TH INTERNATIONAL SOC DESIGN CONFERENCE, ISOCC, 2023, : 69 - 70
[43] An Implementation of Random Single Input Change Technique for Low-Power Test
Wang Yi
Fu Xing-hua
Wang Dai-qiang
2008 2ND INTERNATIONAL CONFERENCE ON ANTI-COUNTERFEITING, SECURITY AND IDENTIFICATION, 2008, : 352 - +
[44] Low power CORDIC implementation using redundant number representation
Schimpfle, CV
Simon, S
Nossek, JA
IEEE INTERNATIONAL CONFERENCE ON APPLICATION-SPECIFIC SYSTEMS, ARCHITECTURES AND PROCESSORS, PROCEEDINGS, 1997, : 154 - 161
[45] Implementation of Low Power Programmable Flash ADC Using IDUDGMOSFET
Mukherjee, Sagar
Dutta, Arka
Roy, Swarnil
Sarkar, Chandan Kumar
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2018, 65 (07) : 844 - 848
[46] An Overview of Low Power Design Implementation of A Subsystem using UPF
Nagendra, Jayam Siva
Ramavenkateswaran, N.
PROCEEDINGS OF THE 5TH INTERNATIONAL CONFERENCE ON INVENTIVE COMPUTATION TECHNOLOGIES (ICICT-2020), 2020, : 1042 - 1047
[47] Low power content addressable memory designing and implementation using voltage swing self adjustable match line technique
Inamanamelluri, Saidulu
Dhanasekaran, D.
Bhaskar, Radhika
SUSTAINABLE COMPUTING-INFORMATICS & SYSTEMS, 2024, 43
[48] Power and Crosstalk Reduction Using Bus Encoding Technique for RLC Modeled VLSI Interconnect
Babu, G. Nagendra
Agarwal, Deepika
Kaushik, B. K.
Manhas, S. K.
TRENDS IN NETWORKS AND COMMUNICATIONS, 2011, 197 : 424 - 434
[49] Low power sequential circuit design by using priority encoding and clock gating
Wu, XW
Pedram, M
ISLPED '00: PROCEEDINGS OF THE 2000 INTERNATIONAL SYMPOSIUM ON LOW POWER ELECTRONICS AND DESIGN, 2000, : 143 - 148
[50] A low power crosstalk-free bus encoding using genetic algorithm
Vinh, Truong Quang
Kim, Young-Chul
2008 IEEE/ACS INTERNATIONAL CONFERENCE ON COMPUTER SYSTEMS AND APPLICATIONS, VOLS 1-3, 2008, : 69 - 73

← 1 2 3 4 5 →