Low-power and high-speed architecture for EBCOT block in JPEG2000 system

In this paper we propose a novel low power and high-speed architecture for the context formation sub block in tier-1 block of JPEG2000 system. The proposed architecture is inspired from the statistical analysis results on 20 images with 512*512 bits each. The behavior of the proposed architecture is compared to the speedy architecture proposed in Ill. For code block size of 64*64 bits, the timing and power consumption analysis show that the proposed architecture can reduce the power consumption by approximately 21% and increase the processing speed by approximately 46% with respect to the reference architecture.