Design framework for JPEG2000 system architecture

被引：0
|
作者：
Tsutsui, Hiroshi [1 ]
Masuzaki, Takahiko
Hayashi, Yoshiteru
Taki, Yoshitaka
Izumi, Tomonori
Onoye, Takao
Nakamura, Yukihiro
机构：
[1] Kyoto Univ, Dept Commun & Comp Engn, Sakyo Ku, Kyoto 6068501, Japan
[2] Osaka Univ, Dept Informat Syst Engn, Suita, Osaka 5650871, Japan
来源：
INTELLIGENT AUTOMATION AND SOFT COMPUTING | 2006年 / 12卷 / 03期
基金：
日本学术振兴会;
关键词：
JPEG2000; design framework; system architecture; configurable processor; Xtensa;
D O I：
10.1080/10798587.2006.10642936
中图分类号：
TP [自动化技术、计算机技术];
学科分类号：
0812 ;
摘要：
For the exploration of system architecture dedicated to JPEG2000 coding, decoding and codec, a novel design framework is constructed. In order to utilize the scalability of JPEG2000 algorithm aggressively in system implementation, three types of modules are prepared for JPEG2000 coding/decoding/codec processes, i.e. software, software accelerated with user-defined instructions, and dedicated hardware. Specifically, dedicated hardware modules for forward and inverse discrete wavelet transformation (shortly DWT), entropy coder, entropy decoder, and entropy codec as well as software acceleration for the DWT process arc devised to be used in the framework. Furthermore, a JPEG2000 encoder LSI, which consists of a configurable processor Xtensa, the DWT module, and the entropy coder, is fabricated to exemplify the system implementation designed through the use of proposed framework.
引用
收藏
页码：331 / 343
页数：13
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