Novel architecture of EBC for JPEG2000

被引：0

作者：

Gautam, A ^{[1
]}

Madhuri, AG ^{[1
]}

Khandelwal, P ^{[1
]}

Aditya, KP ^{[1
]}

Desai, M ^{[1
]}

Padma, K ^{[1
]}

Dutt, M ^{[1
]}

Bhatia, R ^{[1
]}

机构：

[1] Dhirubhai Ambani Inst Informat & Commun Technol, Dept VLSI Design, Gandhi Sagar, Gujarat, India

来源：

19TH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS | 2005年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

The paper presents a novel architecture of EBC (Embedded Block Coding) for JPEG2000. It presents three speed-up methods: bit-plane parallelization, three stage pipelined architecture of Context Formation block and three stage pipelined architecture of MQ encoder block. The proposed design would consequently enhance the throughput and reduce latency, enabling high speed compression. The synthesis and implementation of the design was clone on 0.13 mu technology using Cadence RTL Compiler.

引用

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页码：530 / 533

页数：4

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