Extremely Scaled Gate-First High-k/Metal Gate Stack with EOT of 0.55 nm Using Novel Interfacial Layer Scavenging Techniques for 22nm Technology Node and Beyond

被引：0

作者：

Choi, K. ^{[1
]}

Jagannathan, H. ^{[2
]}

Choi, C. ^{[3
]}

Edge, L. ^{[2
]}

Ando, T. ^{[3
]}

Frank, M. ^{[3
]}

Jamison, P. ^{[3
]}

Wang, M. ^{[3
]}

Cartier, E. ^{[3
]}

Zafar, S. ^{[3
]}

Bruley, J. ^{[3
]}

Kerber, A. ^{[1
]}

Linder, B. ^{[3
]}

Callegari, A. ^{[3
]}

Yang, Q. ^{[3
]}

Brown, S. ^{[3
]}

Stathis, J. ^{[3
]}

Iacoponi, J. ^{[1
]}

Paruchuri, V. ^{[2
]}

Narayanan, V. ^{[3
]}

机构：

[1] Adv Micro Devices Inc, Yorktown Hts, NY 10598 USA

[2] Albany Nanotech, IBM Res Div, Albany, NY 12203 USA

[3] TJ Watson Res Ctr, IBM Res Div, Yorktown Hts, NY 10598 USA

来源：

2009 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS | 2009年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We report for the first time that extreme EOT scaling and low n/p V(TH)s can be achieved simultaneously. Underlying mechanisms that enable EOT scaling and EWF tuning are explained and the fundamental device parameters including reliability of the extremely scaled devices are discussed. Record low gate leakage, appropriately low V(TH)s and competitive carrier mobilities in this work demonstrate the gate stack technology that is consistent with the sub-22 nm node requirements.

引用

页码：A138 / A139

页数：2

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