32nm Gate-First High-k/Metal-Gate Technology for High Performance Low Power Applications

被引：0

作者：

Diaz, C. H. ^{[1
]}

Goto, K. ^{[1
]}

Huang, H. T. ^{[1
]}

Yasuda, Yuri ^{[1
]}

Tsao, C. P. ^{[1
]}

Chu, T. T. ^{[1
]}

Lu, W. T. ^{[1
]}

Chang, Vincent ^{[1
]}

Hou, Y. T. ^{[1
]}

Chao, Y. S. ^{[1
]}

Hsu, P. F. ^{[1
]}

Chen, C. L. ^{[1
]}

Lin, K. C. ^{[1
]}

Ng, J. A. ^{[1
]}

Yang, W. C. ^{[1
]}

Chen, C. H. ^{[1
]}

Peng, Y. H. ^{[1
]}

Chen , C. J. ^{[1
]}

Chen, C. C. ^{[1
]}

Yu, M. H. ^{[1
]}

Yeh, L. Y. ^{[1
]}

You, K. S. ^{[1
]}

Chen, K. S. ^{[1
]}

Thei, K. B. ^{[1
]}

Lee, C. H. ^{[1
]}

Yang, S. H. ^{[1
]}

Cheng, J. Y. ^{[1
]}

Huang, K. T. ^{[1
]}

Liaw, J. J. ^{[1
]}

Ku, Y. ^{[1
]}

Jang, S. M. ^{[1
]}

Chuang, H. ^{[1
]}

Liang, M. S. ^{[1
]}

机构：

[1] Taiwan Semicond Mfg Co Ltd, Res & Dev, Hsinchu, Taiwan

来源：

IEEE INTERNATIONAL ELECTRON DEVICES MEETING 2008, TECHNICAL DIGEST | 2008年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A 32nm gate-first high-k/metal-gate technology is demonstrated with the strongest performance reported to date to the best of our knowledge. Drive currents of 1340/940 mu A/mu m (n/p) are achieved at I-off=100 nA/mu m, V-dd=1V, 30nm physical gate length and 130nm gate pitch. This technology also provides a high-Vt solution for high-performance low-power applications with its high drive currents of 1020/700 mu A/g mu m (n/p) at total I-off similar to 1 nA/mu m @ V-dd = 1V Low sub-threshold leakage was achieved while successfully containing I-boff and I-goff well below 1nA/um. Ultra high density 0.15 um(2) SRAM cell is fabricated by high NA 193nm immersion lithography. Functional 2Mb SRAM test-chip in 32nm design rule has been demonstrated with a controllable manufacturing window.

引用

页码：629 / 632

页数：4

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