A cost effective 32nm high-k/metal gate CMOS technology for low power applications with single-metal/gate-first process

被引：0

作者：

Chen, X. ^{[1
]}

Samavedam, S. ^{[2
]}

Narayanan, V. ^{[1
]}

Stein, K. ^{[1
]}

Hobbs, C. ^{[2
]}

Baiocco, C. ^{[1
]}

Li, W. ^{[1
]}

Jaeger, D. ^{[1
]}

Zaleski, M. ^{[2
]}

Yang, H. S. ^{[1
]}

Kim, N. ^{[3
]}

Lee, Y. ^{[1
]}

Zhang, D. ^{[2
]}

Kang, L. ^{[2
]}

Chen, J. ^{[3
]}

Zhuang, H. ^{[4
]}

Sheikh, A. ^{[1
]}

Wallner, J. ^{[1
]}

Aquilino, M. ^{[1
]}

Han, J. ^{[4
]}

Jin, Z. ^{[1
]}

Li, J. ^{[1
]}

Massey, G. ^{[1
]}

Kalpat, S. ^{[1
]}

Jha, R. ^{[1
]}

Moumen, N. ^{[1
]}

Mo, R. ^{[1
]}

Kirshnan, S. ^{[1
]}

Wang, X. ^{[1
]}

Chudzik, M. ^{[1
]}

Chowdhury, M. ^{[2
]}

Nair, D. ^{[1
]}

Reddy, C. ^{[2
]}

Teh, Y. W. ^{[3
]}

Kothandaraman, C. ^{[1
]}

Coolbaugh, D. ^{[1
]}

Pandey, S. ^{[3
]}

Tekleab, D. ^{[3
]}

Thean, A. ^{[2
]}

Sherony, M. ^{[1
]}

Lage, C. ^{[2
]}

Sudijono, J. ^{[3
]}

Lindsay, R. ^{[4
]}

Ku, J. H. ^{[5
]}

Khare, M. ^{[1
]}

Steegen, A. ^{[1
]}

机构：

[1] IBM Corp, Semicond Res & Dev Ctr, Hopewell Jct, NY 12533 USA

[2] Freescale Semicond, Hyderabad, Andhra Pradesh, India

[3] Chartered Semicond Mfg Ltd, Woodland Hills, CA USA

[4] Infineon Technol AG, Neuherberg, Germany

[5] Samsung Elect Co Ltd, Suwon, South Korea

来源：

2008 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS | 2008年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

For the first time, we have demonstrated a 32nm high-k/metal gate (HK-MG) low power CMOS platform technology with low standby leakage transistors and functional high-density SRAM with a cell size of 0.157 mu m(2). Record NMOS/PMOS drive currents of 1000/575 mu A/mu m, respectively, have been achieved at 1 nA/mu m off-current and 1.1V V-dd with a low cost process. With this high performance transistor, V-dd can be further scaled to 1.0V for active power reduction. Through aggressive EOT scaling and band-edge work-function metal gate stacks, appropriate Vts and superior short channel control has been achieved for both NMOS and PMOS at L-gate=30nm. Compared to SiON-Poly, 30% RO delay reduction has been demonstrated with HK-MG devices. 40% Vt mismatch reduction has been shown with the Tinv scaling. Furthermore, it has been shown that the 1/f noise and transistor reliability exceed the technology requirements.

引用

页码：88A / 89A

页数：2

共 50 条

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Chen, X.
Samavedam, S.
Narayanan, V.
Stein, K.
Hobbs, C.
Baiocco, C.
Li, W.
Jaeger, D.
Zaleski, M.
Yang, H. S.
Kim, N.
Lee, Y.
Zhang, D.
Kang, L.
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Zhuang, H.
Sheikh, A.
Wallner, J.
Aquilino, M.
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Jin, Z.
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Massey, G.
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