Gate first band edge high-k/metal stacks with EOT=0.74nm for 22nm node nFETs

被引：2
|
作者：
Huang, J. [1 ]
Kirsch, P. D. [1 ]
Hussain, M. [1 ]
Heh, D. [1 ]
Sivasubramani, P. [1 ]
Young, C. [1 ]
Gilmer, D. C. [1 ]
Park, C. S. [1 ]
Tan, Y. N. [1 ]
Park, C. [1 ]
Harris, H. R. [2 ]
Majhi, P. [3 ]
Bersuker, G. [1 ]
Lee, B. H. [1 ]
Tseng, H. -H. [1 ]
Jammy, R. [4 ]
机构：
[1] SEMATECH, 2706 Montopolis Dr, Austin, TX 78741 USA
[2] AMD, Sunnyvale, CA USA
[3] Intel, Santa Clara, CA USA
[4] IBM Corp, New York, NY USA
来源：
2008 INTERNATIONAL SYMPOSIUM ON VLSI TECHNOLOGY, SYSTEMS AND APPLICATIONS (VLSI-TSA), PROCEEDINGS OF TECHNICAL PROGRAM | 2008年
关键词：
D O I：
10.1109/VTSA.2008.4530842
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
We demonstrate for the first time a gate first high-k/metal gate (MG) nFET with EOT=0.74nm (T-inv=1.15mn), low V-t =0.30V, high performance [I-on/I-off=1310(mu A/um) at 100(nA/um)], low leakage (> 200x reduction vs. SiO2/PolySi) and good PBTI. Low-k interface layer scaling and high-k La-doping enable this desirable EOT and V-t. SiON/HfLaSiON can give similar interface quality as SiO2/HfSiON. Device performance was further improved 5% by strain engineering.
引用
收藏
页码：152 / +
页数：2
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