Arithmetic-oriented multiple-valued logic-in-memory VLSI based on current-mode logic

A new logic-in-memory architecture, in which storage elements are distributed over a current-mode logic-circuit plane by the use of floating-gate MOS transistors, as proposed to realize a compact arithmetic VLSI system. Since not only a storage function but also a voltage-mode linear summation and a voltage-to-current conversion are merged into a single floating-gate MOS transistor, the logic-in-memory VLSI becomes very compact with a high-performance capability. As an example, at is demonstrated that the effective chap area of the proposed four-valued current-mode full adder is reduced to 5% tinder the same switching speed in comparison with the corresponding binary CMOS implementation.