Digital Embedded Test Instrument for On-Chip Phase Noise Testing of Analog/RF Integrated Circuits

被引：0

作者：

Azais, Florence ^{[1
]}

David-Grignot, Stephane ^{[1
,2
]}

Latorre, Laurent ^{[1
]}

Lefevre, Francois ^{[2
]}

机构：

[1] Univ Montpellier, CNRS, LIRMM, 161 Rue Ada, F-34095 Montpellier, France

[2] NXP Semicond, 2 Espl Anton Phillips, F-14000 Caen, France

来源：

JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS | 2016年 / 25卷 / 03期

关键词：

Noise measurement; phase noise; analog/IF signals; 1-bit acquisition; digital signal processing; built-in-self-test; BIST; test cost reduction;

D O I：

10.1142/S0218126616400144

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper presents a digital embedded test instrument (ETI) for on-chip phase noise (PN) testing of analog/RF integrated circuits. The technique relies on 1-bit signal acquisition and dedicated processing to compute a digital signature related to the PN level. An appropriate algorithm based on on-the-fly processing of the 1-bit signal is defined in order to implement the BIST module with minimal hardware resources. Its implementation in CMOS 140nm technology occupies only 7,885 mu m(2), which represents an extremely small silicon area. Hardware measurements are performed on an FPGA prototype that validates the proposed instrument.

引用

页数：18

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