A simple noise modeling based testing of CMOS analog integrated circuits

A technique for testing CMOS analog integrated circuits is presented which is based on an analysis of the noise behavior of the circuit under test (CUT). The technique is simple and new. The CUT in the present work is an integrated CMOS amplifier circuit designed in a standard 1.5 mu m n-well CMOS process for operation at +/- 2.5 V. The bridging faults simulating possible manufacturing defects have been introduced using fault injection transistors. The faults in the CUT are detected by observing the variation in the noise at the output of CUT, which is the sum of noise contributed from each component in the circuit. An analytical noise model of the CUT has been developed with and without faults and results are compared with the corresponding data obtained from the simulation studies using SPICE.