A simple noise modeling based testing of CMOS analog integrated circuits

被引：0

作者：

Yellampalli, S ^{[1
]}

Srivastava, A ^{[1
]}

机构：

[1] Louisiana State Univ, Dept Elect & Comp Engn, Baton Rouge, LA 70803 USA

来源：

NOISE IN DEVICES AND CIRCUITS III | 2005年 / 5844卷

关键词：

CMOS amplifier; MOS noise modeling; fault injection transistor; CMOS analog testing;

D O I：

10.1117/12.609253

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A technique for testing CMOS analog integrated circuits is presented which is based on an analysis of the noise behavior of the circuit under test (CUT). The technique is simple and new. The CUT in the present work is an integrated CMOS amplifier circuit designed in a standard 1.5 mu m n-well CMOS process for operation at +/- 2.5 V. The bridging faults simulating possible manufacturing defects have been introduced using fault injection transistors. The faults in the CUT are detected by observing the variation in the noise at the output of CUT, which is the sum of noise contributed from each component in the circuit. An analytical noise model of the CUT has been developed with and without faults and results are compared with the corresponding data obtained from the simulation studies using SPICE.

引用

页码：276 / 283

页数：8

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