Modeling substrate noise generation in CMOS digital integrated circuits

被引：12

作者：

Nagata, M ^{[1
]}

Morie, T ^{[1
]}

Iwata, A ^{[1
]}

机构：

[1] Hiroshima Univ, Integrated Syst Lab, Higashihiroshima 7398526, Japan

来源：

PROCEEDINGS OF THE IEEE 2002 CUSTOM INTEGRATED CIRCUITS CONFERENCE | 2002年

关键词：

D O I：

10.1109/CICC.2002.1012889

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

A time-series divided parasitic capacitance model accurately simulates substrate noise generation of practical CMOS digital integrated circuits in time domain. The simulation of a 0.25-mum z80 micro-controller with 62.5-MHz clock frequency costs less than 10 sec. per a clock cycle including the model generation. Simulated substrate noise well consists with 200-ps 100-muV resolution measurements in wave-shapes validated for clock frequency up to 125 MHz and shows the peak-amplitude error of less than 2% against supply-voltage scaling from 2.5 V to 1.6 V.

引用

页码：501 / 504

页数：4

共 50 条

[1] Modeling and Simulation of Substrate Noise in Integrated RF CMOS Circuits
Lin, L.
Xiong, J.
Mathis, W.
ADVANCES IN RADIO SCIENCE, 2009, 7 : 163 - 168
[2] Emulation of high-frequency substrate noise generation in CMOS digital circuits
Shimazaki, Shunsuke
Taga, Shota
Makita, Tetsuya
Azuma, Naoya
Miura, Noriyuki
Nagata, Makoto
JAPANESE JOURNAL OF APPLIED PHYSICS, 2014, 53 (04)
[3] Active suppression of substrate noise in CMOS integrated circuits
Blakiewicz, G.
MIXDES 2007: PROCEEDINGS OF THE 14TH INTERNATIONAL CONFERENCE ON MIXED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS:, 2007, : 219 - 224
[4] Modeling of substrate noise effects in dynamic CMOS circuits
Gosavi, Sagar. R.
Al-Assadi, Waleed K.
Burugapalli, Sasikiran
2008 IEEE REGION 5 CONFERENCE, 2008, : 54 - 59
[5] Modeling of Substrate Noise in Monolithic Integrated Circuits
Manetas, George
Cangellaris, Andreas C.
2010 TOPICAL MEETING ON SILICON MONOLITHIC INTEGRATED CIRCUITS IN RF SYSTEMS, 2010, : 172 - +
[6] Modeling of Power Noise Generation in Standard-Cell Based CMOS Digital Circuits
Matsuno, Tetsuro
Kosaka, Daisuke
Nagata, Makoto
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, 2010, E93A (02) : 440 - 447
[7] Test circuits for substrate noise evaluation in CMOS digital ICs
Nagata, M
Ohmoto, T
Nagai, J
Morie, T
Iwata, A
PROCEEDINGS OF THE ASP-DAC 2001: ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE 2001, 2001, : 13 - 14
[8] Simulation and modeling of substrate noise generation from synchronous and asynchronous digital logic circuits
Harken, Christopher
Le, Jim
Fiez, Terri S.
Mayaram, Kartikeya
PROCEEDINGS OF THE IEEE 2007 CUSTOM INTEGRATED CIRCUITS CONFERENCE, 2007, : 845 - 848
[9] Physical design guides for substrate noise reduction in CMOS digital circuits
Nagata, M
Nagai, J
Hijikata, K
Morie, T
Iwata, A
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2001, 36 (03) : 539 - 549
[10] An experimental comparison of substrate noise generated by CMOS and by low-noise digital circuits
Albuquerque, EFM
Silva, MM
2004 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL 2, PROCEEDINGS, 2004, : 481 - 484

← 1 2 3 4 5 →