Modeling substrate noise generation in CMOS digital integrated circuits

A time-series divided parasitic capacitance model accurately simulates substrate noise generation of practical CMOS digital integrated circuits in time domain. The simulation of a 0.25-mum z80 micro-controller with 62.5-MHz clock frequency costs less than 10 sec. per a clock cycle including the model generation. Simulated substrate noise well consists with 200-ps 100-muV resolution measurements in wave-shapes validated for clock frequency up to 125 MHz and shows the peak-amplitude error of less than 2% against supply-voltage scaling from 2.5 V to 1.6 V.