On-Chip Power Noise Measurements of High-Frequency CMOS Digital Circuits

被引：0

作者：

Matsuno, Tetsuro ^{[1
]}

Nagata, Makoto ^{[1
]}

机构：

[1] Kobe Univ, Dept Comp Sci & Syst Engn, Nada Ku, Kobe, Hyogo 6578501, Japan

来源：

2009 INTERNATIONAL SOC DESIGN CONFERENCE (ISOCC 2009) | 2009年

关键词：

D O I：

10.1109/SOCDC.2009.5423904

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

On-chip power and substrate noise measurements were performed on shift registers in a 90-nm CMOS technology, with operating frequencies ranging from 100 MHz up to 1.2 GHz. Combined on-chip digitization and off-chip timing generation achieves the effective measurement bandwidth as high as 1.3 GHz. It was experimentally observed that dynamic components of power noise decrease for the higher operating frequencies.

引用

页码：198 / 201

页数：4

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