Predictability in RT-Level designs

被引:2
|
作者
Srivastava, A [1 ]
Kursun, E [1 ]
Sarrafzadeh, M [1 ]
机构
[1] Univ Calif Los Angeles, Dept Comp Sci, Los Angeles, CA 90095 USA
关键词
predictability; power estimation; high level synthesis; knapsack;
D O I
10.1142/S0218126602000483
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
The primary objective of this paper is to provide an initial impetus to predictability driven design flow. Predictability is the quantified form of accuracy. The novelty lies in defining and using the idea of predictability. In order to illustrate the basic concepts we focus on the power estimation problem in RT-Level designs. Our experiments showed that predictability at RT-Level could be improved by making the resource delay constraints more stringent. This procedure may come with increased power dissipation. We present an optimal pseudo-polynomial time algorithm to optimize predictability while keeping the increase in power dissipation within a budget. We further extend this algorithm to generate an E-approximate solution in polynomial time where E is a user defined parameter. The algorithm probably generates solutions that differ at-most epsilonC(max) from the optimal. The future work would include extending the concept of predictability to other levels of design flow and other cost function. We envision a design automation system which does effective tradeoff between predictability and cost hence enabling efficient design exploration.
引用
收藏
页码:323 / 332
页数:10
相关论文
共 50 条
  • [31] A Benchmark Suite of RT-level Hardware Trojans for Pipelined Microprocessor Cores
    Damljanovic, Aleksa
    Ruospo, Annachiara
    Sanchez, Ernesto
    Squillero, Giovanni
    2021 24TH INTERNATIONAL SYMPOSIUM ON DESIGN AND DIAGNOSTICS OF ELECTRONIC CIRCUITS & SYSTEMS (DDECS), 2021, : 51 - 56
  • [32] 集成电路RT-Level功耗估计方法概论
    吴凯
    林争辉
    电路与系统学报, 2004, (01) : 95 - 100
  • [33] An RT-level concurrent error detection technique for data dominated systems
    Goloubeva, O
    Reorda, MS
    Violante, M
    9TH IEEE INTERNATIONAL ON-LINE TESTING SYMPOSIUM, PROCEEDINGS, 2003, : 159 - 159
  • [34] RT-Level Deviation-Based Grading of Functional Test Sequences
    Fang, Hongxia
    Chakrabarty, Krishnendu
    Jas, Abhijit
    Patil, Srinivas
    Tirumurti, Chandra
    2009 27TH IEEE VLSI TEST SYMPOSIUM, PROCEEDINGS, 2009, : 264 - +
  • [35] Cycle-accurate macro-models for RT-level power analysis
    Qiu, QR
    Wu, Q
    Pedram, M
    Ding, CS
    1997 INTERNATIONAL SYMPOSIUM ON LOW POWER ELECTRONICS AND DESIGN, PROCEEDINGS, 1997, : 125 - 130
  • [36] WaLo: Security Primitive Generator for RT-Level Logic Locking and Watermarking
    Kuai, Jun
    He, Jiaji
    Ma, Haocheng
    Zhao, Yiqiang
    Hou, Yumin
    Jin, Yier
    PROCEEDINGS OF THE 2020 ASIAN HARDWARE ORIENTED SECURITY AND TRUST SYMPOSIUM (ASIANHOST), 2020,
  • [37] Quick generation of temporal power waveforms for RT-level hard macros
    Benini, L
    DeMicheli, G
    Macii, E
    Poncino, M
    Scarsi, R
    SECOND ANNUAL IEEE INTERNATIONAL CONFERENCE ON INNOVATIVE SYSTEMS IN SILICON, 1997 PROCEEDINGS, 1997, : 331 - 337
  • [38] Observability-enhanced statement coverage evaluation method at RT-level
    Advanced Test Technology Laboratory, Institute of Computing Technology, Chinese Academy of Sciences, Beijing 100080, China
    不详
    Jisuanji Fuzhu Sheji Yu Tuxingxue Xuebao, 2006, 1 (62-68):
  • [39] Accurate data path models for fast RT-level power estimation
    Theoharis, S
    Theodoridis, G
    Merakos, P
    Goutis, C
    IEE PROCEEDINGS-COMPUTERS AND DIGITAL TECHNIQUES, 2000, 147 (04): : 209 - 214
  • [40] Concurrent skew and control step assignments in RT-level datapath synthesis
    Obata, Takayuki
    Kaneko, Mineo
    PROCEEDINGS OF 2008 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-10, 2008, : 2018 - 2021