共 15 条
- [1] Hierarchical constraint conscious RT-level test generation [J]. EUROMICRO SYMPOSIUM ON DIGITAL SYSTEM DESIGN, PROCEEDINGS, 2003, : 312 - 318
- [2] Power Modeling on FPGA: A Neural Model for RT-Level Power Estimation [J]. 2018 ACM INTERNATIONAL CONFERENCE ON COMPUTING FRONTIERS, 2018, : 309 - 313
- [3] Low-power RT-level synthesis techniques: a tutorial [J]. IEE PROCEEDINGS-COMPUTERS AND DIGITAL TECHNIQUES, 2005, 152 (03): : 333 - 343
- [4] Statistical sampling and regression analysis for RT-level power evaluation [J]. 1996 IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN - DIGEST OF TECHNICAL PAPERS, 1996, : 583 - 588
- [5] RT-Level Vector Selection for Realistic Peak Power Simulation [J]. GLSVLSI'07: PROCEEDINGS OF THE 2007 ACM GREAT LAKES SYMPOSIUM ON VLSI, 2007, : 576 - 581
- [6] Automatic test program generation from RT-level microprocessor descriptions [J]. PROCEEDING OF THE 2002 3RD INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN, 2002, : 120 - 125
- [8] Accurate data path models for fast RT-level power estimation [J]. IEE PROCEEDINGS-COMPUTERS AND DIGITAL TECHNIQUES, 2000, 147 (04): : 209 - 214
- [9] Cycle-accurate macro-models for RT-level power analysis [J]. 1997 INTERNATIONAL SYMPOSIUM ON LOW POWER ELECTRONICS AND DESIGN, PROCEEDINGS, 1997, : 125 - 130