Predictability in RT-Level designs

被引:2
|
作者
Srivastava, A [1 ]
Kursun, E [1 ]
Sarrafzadeh, M [1 ]
机构
[1] Univ Calif Los Angeles, Dept Comp Sci, Los Angeles, CA 90095 USA
关键词
predictability; power estimation; high level synthesis; knapsack;
D O I
10.1142/S0218126602000483
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
The primary objective of this paper is to provide an initial impetus to predictability driven design flow. Predictability is the quantified form of accuracy. The novelty lies in defining and using the idea of predictability. In order to illustrate the basic concepts we focus on the power estimation problem in RT-Level designs. Our experiments showed that predictability at RT-Level could be improved by making the resource delay constraints more stringent. This procedure may come with increased power dissipation. We present an optimal pseudo-polynomial time algorithm to optimize predictability while keeping the increase in power dissipation within a budget. We further extend this algorithm to generate an E-approximate solution in polynomial time where E is a user defined parameter. The algorithm probably generates solutions that differ at-most epsilonC(max) from the optimal. The future work would include extending the concept of predictability to other levels of design flow and other cost function. We envision a design automation system which does effective tradeoff between predictability and cost hence enabling efficient design exploration.
引用
收藏
页码:323 / 332
页数:10
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