Behavioral emulation of synthesized RT-level descriptions using VLIW architectures

被引：0

作者：

Buchholz, T ^{[1
]}

Haug, G ^{[1
]}

Kebschull, U ^{[1
]}

Koch, G ^{[1
]}

Rosenstiel, W ^{[1
]}

机构：

[1] Forschungszentrum Informat, D-76131 Karlsruhe, Germany

来源：

NINTH INTERNATIONAL WORKSHOP ON RAPID SYSTEM PROTOTYPING - PROCEEDINGS | 1998年

关键词：

D O I：

10.1109/IWRSP.1998.676671

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This article describes techniques that allow VLIW architectures to be used for the behavioural emulation of RT level descriptions. Starting point of the techniques is a behavioural description at algorithmic level e.g. VHDL. This description is transformed into RT level descriptions of the datapath and controller. The controller is given as a finite state machine. We show how to map these descriptions onto assembly code that can be executed on a VLIW microprocessor. We found the Texas instruments TMS320C6x series of DSP processors to be suitable candidates for the mapping.

引用

页码：70 / 75

页数：6

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