Timing, power and noise optimization for simultaneous switching in VLSI circuits.

This paper describes a technique to aggregate the best position such that the system requirement is satisfied. A key feature of the approach is that it provides an accurate way to estimate timing, power dissipation, and noise based on quality of library for simultaneous switching and choose the best position in setup region for sequential circuits such that the system constraints (i.e. power, delay or noise) are satisfied based on integer linear programming (ILP) exploration model. Results on a large number of benchmark sequential circuits and combinatorial circuits confirm that the technique yields accurate position based on the constraints on performance metrics - delay, power, and noise for sequential circuit.