Switching noise reduction in clock distribution in mixed-mode VLSI circuits

One of the most important sources of switching noise in large VLSI circuits is the clock-driven circuitry and the clock generation and distribution logic. It is well known for the mixed-signal community that harmonics of clock signal are easily injected in the analog part. This paper analyzes how some actuations like the insertion of buffers, the suited, placement and routing of the clock tree cells, as well as the suited sizing of devices can save switching noise. In fact, different solutions for the clocking logic generate very different results for switching noise.