An ultra low voltage SOI CMOS pass-gate logic

被引：0
|
作者：
Fuse, T [1 ]
Oowaki, Y [1 ]
Terauchi, M [1 ]
Watanabe, S [1 ]
Yoshimi, M [1 ]
Ohuchi, K [1 ]
Matsunaga, J [1 ]
机构：
[1] TOSHIBA CO LTD, MICROELECT ENGN LAB, KAWASAKI, KANAGAWA 210, JAPAN
来源：
IEICE TRANSACTIONS ON ELECTRONICS | 1997年 / E80C卷 / 03期
关键词：
SOI; 0.5 V operation; ultra low voltage; pass-gate logic; body bias control;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
An ultra low voltage CMOS pass-gate logic using body-bias controlled SOI MOSFETs has been developed. The logic is composed of gate-body connected SOI pass-gates and a CMOS buffer with the body-bias controlled by the complementary double-rail input. The full-adder using the proposed logic improved the lowest operation voltage by 27%, compared with the SOI CPL (Complementary Pass-Gate Logic). For a 16 X 16 bit multiplier, the power-delay product achieved 70 pJ (including 50 pF I/O) at 0.5 V power supply, which was more than 1 order of magnitude improvement over the bulk CPL.
引用
收藏
页码：472 / 477
页数：6
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