An ultra low voltage SOI CMOS pass-gate logic

被引：0

作者：

Fuse, T ^{[1
]}

Oowaki, Y ^{[1
]}

Terauchi, M ^{[1
]}

Watanabe, S ^{[1
]}

Yoshimi, M ^{[1
]}

Ohuchi, K ^{[1
]}

Matsunaga, J ^{[1
]}

机构：

[1] TOSHIBA CO LTD, MICROELECT ENGN LAB, KAWASAKI, KANAGAWA 210, JAPAN

来源：

IEICE TRANSACTIONS ON ELECTRONICS | 1997年 / E80C卷 / 03期

关键词：

SOI; 0.5 V operation; ultra low voltage; pass-gate logic; body bias control;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

An ultra low voltage CMOS pass-gate logic using body-bias controlled SOI MOSFETs has been developed. The logic is composed of gate-body connected SOI pass-gates and a CMOS buffer with the body-bias controlled by the complementary double-rail input. The full-adder using the proposed logic improved the lowest operation voltage by 27%, compared with the SOI CPL (Complementary Pass-Gate Logic). For a 16 X 16 bit multiplier, the power-delay product achieved 70 pJ (including 50 pF I/O) at 0.5 V power supply, which was more than 1 order of magnitude improvement over the bulk CPL.

引用

页码：472 / 477

页数：6

共 50 条

[21] Low Voltage Precharge CMOS Logic
Berg, Yngvar
Mirmotahari, Omid
PROCEEDINGS OF THE 2009 IEEE SYMPOSIUM ON DESIGN AND DIAGNOSTICS OF ELECTRONIC CIRCUITS AND SYSTEMS, 2009, : 140 - 143
[22] DIFFERENTIAL HIGH SPEED ULTRA LOW-VOLTAGE PASS TRANSISTOR BOOLEAN LOGIC
Berg, Y.
2013 IEEE FAIBLE TENSION FAIBLE CONSOMMATION (FTFC), 2013,
[23] A 0.5V 200MHz 1-stage 32b ALU using a body bias controlled SOI pass-gate logic
Fuse, T
Oowaki, Y
Yamada, T
Kamoshida, M
Ohta, M
Shino, T
Kawanaka, S
Terauchi, M
Yoshida, T
Matsubara, G
Yoshioka, S
Watanabe, S
Yoshimi, M
Ohuchi, K
Manabe, S
1997 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE - DIGEST OF TECHNICAL PAPERS, 1997, 40 : 286 - 287
[24] Ultra low voltage CMOS gates
Berg, Yngvar
Mirmotahari, Omid
Norseng, Per Andreas
Aunet, Snorre
2006 13TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS, VOLS 1-3, 2006, : 818 - 821
[25] Low-voltage RF circuits in CMOS/SOI
Kodate, Junichi
Harada, Mitsuru
Tsukahara, Tsunco
NTT R and D, 2001, 50 (11): : 880 - 884
[26] STATIC ULTRA-LOW-VOLTAGE HIGH-SPEED CMOS LOGIC AND LATCHES
Berg, Y.
PROCEEDINGS OF THE 2010 18TH IEEE/IFIP INTERNATIONAL CONFERENCE ON VLSI AND SYSTEM-ON-CHIP, 2010, : 115 - 118
[27] Novel bootstrapped CMOS differential logic family for ultra-low voltage SoCs
Jung, Byung-Hwa
Kang, Sung-Chan
Oh, Jae-Hyuk
Park, Yoon-Suk
Kim, Yong-Ki
Kang, Yong-Gu
Kim, Jong-Woo
Kong, Bai-Sun
IEICE ELECTRONICS EXPRESS, 2008, 5 (18): : 711 - 717
[28] Back gate bias method of threshold voltage control for the design of low voltage CMOS ternary logic circuits
Srivastava, A
MICROELECTRONICS RELIABILITY, 2000, 40 (12) : 2107 - 2110
[29] Realization of gate performance using Hybrid SET -CMOS Pass transistor based logic gate
Jana, Anindya
Naskar, Kousik
Sarkhel, Saheli
Manna, Bibhas
Sing, J. K.
Sarkar, Subir Kumar
2013 ANNUAL INTERNATIONAL CONFERENCE ON EMERGING RESEARCH AREAS & 2013 INTERNATIONAL CONFERENCE ON MICROELECTRONICS, COMMUNICATIONS & RENEWABLE ENERGY (AICERA/ICMICR), 2013,
[30] A 16nm Configurable Pass-Gate Bit-Cell Register File for Quantifying the VMIN Advantage of PFET versus NFET Pass-Gate Bit Cells
Jeong, Jihoon
Atallah, Francois
Hoan Nguyen
Puckett, Josh
Bowman, Keith
Hansquine, David
2015 IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE (CICC), 2015,

← 1 2 3 4 5 →