STATIC ULTRA-LOW-VOLTAGE HIGH-SPEED CMOS LOGIC AND LATCHES

被引：0
|
作者：
Berg, Y. [1 ]
机构：
[1] Univ Oslo, Dept Informat, N-0316 Oslo, Norway
来源：
PROCEEDINGS OF THE 2010 18TH IEEE/IFIP INTERNATIONAL CONFERENCE ON VLSI AND SYSTEM-ON-CHIP | 2010年
关键词：
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
In this paper we present timing details for static ultra-low-voltage (ULV) CMOS inverters and latches. The logic presented resemble domino CMOS logic and is more than 10 times as fast as complementary CMOS for very low supply voltages. Static ULV inverters and latches are presented and preliminary simulated data are provided for a 90nm TSMC CMOS process.
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页码：115 / 118
页数：4
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