High-Speed and Ultra-Low-Voltage Divide-by-4/5 Counter for Frequency Synthesizer

被引：1

作者：

Lo, Yu-Lung ^{[1
]}

Yang, Wei-Bin ^{[2
]}

Chao, Ting-Sheng ^{[3
]}

Cheng, Kuo-Hsing ^{[4
]}

机构：

[1] Natl Kaohsiung Marine Univ, Dept Microelect Engn, Kaohsiung 811, Taiwan

[2] Tamkang Univ, Dept Elect Engn, Taipei 251, Taiwan

[3] Ind Technol Res Inst, Hsinchu 300, Taiwan

[4] Natl Cent Univ, Dept Elect Engn, Jhongli 320, Taiwan

来源：

IEICE TRANSACTIONS ON ELECTRONICS | 2009年 / E92C卷 / 06期

关键词：

dynamic D flip-flops; counters; prescalers; ultra-low-voltage design; DUAL-MODULUS PRESCALER; FLIP-FLOPS;

D O I：

10.1587/transele.E92.C.890

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A high-speed and ultra-low-voltage divide-by-4/5 counter with dynamic floating input D flip-flop (DFIDFF) is presented in this paper. The proposed DFIDFF and control logic gates are merged to reduce effective capacitance of internal and external nodes, and increase the operating speed of divide-by-4/5 counter. The proposed divide-by-4/5 counter is fabricated in a 0.13-mu m CMOS process. The measured maximum operating frequency and power consumption of the counter are 600 MHz and 8.35 mu W at a 0.5 V supply voltage. HSPICE simulations demonstrate that the proposed counter (divide-by-4) reduces power-delay product (PDP) by 37%, 71 %, and 57% from those of the TGFF counter, Yang's counter [1] and the E-TSPC counter [2], respectively.

引用

页码：890 / 893

页数：4

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