High-Speed, Modified, Bulk stimulated, Ultra-Low-Voltage, Domino Inverter

In this paper, a new Ultra low voltage (ULV) logic circuit based on the floating gate structure is presented. In this technique we utilized the bulks of the transistors to speed up the circuit. Using the proposed method, the speed of the circuit enhances by connecting the bulks of the evaluating and precharge devices to the clock, power supply (VDD) and input signals. The simulation results for the designed ULV logic in a typical 90nm CMOS technology show more than 40% delay reduction. Higher speed in the lower supply voltages and robustness against process variations are the main advantages of the proposed approach in comparison to the previously reported FGULV and other ULV methods.