High-Speed, Modified, Bulk stimulated, Ultra-Low-Voltage, Domino Inverter

被引：0

作者：

Dadashi, Ali ^{[1
]}

Berg, Yngvar ^{[1
]}

Mirmotahari, Omid ^{[1
]}

机构：

[1] Univ Oslo, Dept Informat, Nanoelect Res Grp, N-0316 Oslo, Norway

来源：

2015 IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI | 2015年

关键词：

Ultra Low Voltage (ULV); Floating Gate; Speed; Bulk;

D O I：

10.1109/ISVLSI.2015.100

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this paper, a new Ultra low voltage (ULV) logic circuit based on the floating gate structure is presented. In this technique we utilized the bulks of the transistors to speed up the circuit. Using the proposed method, the speed of the circuit enhances by connecting the bulks of the evaluating and precharge devices to the clock, power supply (VDD) and input signals. The simulation results for the designed ULV logic in a typical 90nm CMOS technology show more than 40% delay reduction. Higher speed in the lower supply voltages and robustness against process variations are the main advantages of the proposed approach in comparison to the previously reported FGULV and other ULV methods.

引用

页码：86 / 90

页数：5

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