High-Speed Digital Domino Logic for Ultra-Low Supply Voltages

被引：0
|
作者：
Mirmotahari, Omid [1 ]
Berg, Yngvar [1 ]
机构：
[1] Univ Oslo, Dept Informat, Nanoelect, Oslo, Norway
来源：
CIRCUITS SYSTEMS AND SIGNAL PROCESSING | 2017年 / 36卷 / 12期
关键词：
Low-voltage; Dynamic CMOS; High-speed; Differential; Dual-rail;
D O I：
10.1007/s00034-017-0632-4
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
We present a high-speed differential clocked voltage switch logic inverter operating at ultra-low supply voltages (ULV). Simulated data for the new gate are presented and compared to modified clocked voltage switch logic (CVSL). Preliminary measurements for ULV gates are presented. The increase in speed for supply voltages below 300 mV for the ULV gate presented is between 10 and 20 times compared to modified CVSL logic.
引用
收藏
页码：4774 / 4788
页数：15
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