High-Speed Low-Power FinFET Based Domino Logic

被引：0

作者：

Rasouli, Seid Hadi ^{[1
]}

Koike, Hanpei ^{[2
]}

Banerjee, Kaustav ^{[1
]}

机构：

[1] Univ Calif Santa Barbara, Elect & Comp Engn, Santa Barbara, CA 93106 USA

[2] AIST, Nanoelect Res Inst, Electroinformat Grp, Tsukuba, Ibaraki 3058568, Japan

来源：

PROCEEDINGS OF THE ASP-DAC 2009: ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE 2009 | 2009年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper introduces a novel FinFET based domino logic, which exploits the exclusive property of the FinFET device (capacitive coupling between front-gate and back-gate in a four-terminal (4T) FinFET) to simultaneously achieve higher performance and lower power consumption. Using a new implementation of the resistive gate, the keeper device is made weaker at the beginning of the evaluation phase to reduce its contention with the pull-down network, but gradually becomes stronger to provide high noise margin. The strength of the keeper device is controlled by the differential gate voltage, which guarantees low gate-source voltage at the beginning of the evaluation phase and high gate-source voltage during rest of the time.

引用

页码：829 / +

页数：2

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