High-Speed and Low-Power Logic for SAR ADC

High-speed and low-power logic for successive approximation register (SAR) analog-to-digital converter (ADC) is proposed. The proposed SAR logic and the comparator work in parallel mode, which is different from the series mode in the conventional structure. With the delay match of SAR logic and comparator, SAR logic will provide windows to catch the valid results of comparator one by one. Moreover, the proposed logic consists of less D flip-flop (dff) and reduces the capacitive load in the clock and signal path. Finally, an improved self-blocking flip-flop is provided. According to schematic simulation in 28nm COMS technology, it provides >23% faster in one cycle and exhibits <71% power consumption compared with previous structures.