High-Speed Digital Domino Logic for Ultra-Low Supply Voltages

被引：0
|
作者：
Omid Mirmotahari
Yngvar Berg
机构：
[1] University of Oslo,Nanoelectronics, Department of Informatics
来源：
Circuits, Systems, and Signal Processing | 2017年 / 36卷
关键词：
Low-voltage; Dynamic CMOS; High-speed; Differential; Dual-rail;
D O I：
暂无
中图分类号：
学科分类号：
摘要：
We present a high-speed differential clocked voltage switch logic inverter operating at ultra-low supply voltages (ULV). Simulated data for the new gate are presented and compared to modified clocked voltage switch logic (CVSL). Preliminary measurements for ULV gates are presented. The increase in speed for supply voltages below 300 mV for the ULV gate presented is between 10 and 20 times compared to modified CVSL logic.
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收藏
页码：4774 / 4788
页数：14
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