Hardware Implementation of ADABOOST ALGORITHM and Verification

被引：6
|
作者：
Shi, Yuehua [1 ]
Zhao, Feng [1 ]
Zhang, Zhong [1 ]
机构：
[1] Shanghai Jiao Tong Univ, Sch Microelect, Shanghai, Peoples R China
来源：
2008 22ND INTERNATIONAL WORKSHOPS ON ADVANCED INFORMATION NETWORKING AND APPLICATIONS, VOLS 1-3 | 2008年
关键词：
D O I：
10.1109/WAINA.2008.92
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
Adaboost algorithm is difficult to implement on embedded platform for real-time face detection by software due to its high computation load and data throughput. This article presents a cell array architecture using parallel technology. Detection procedure can be greatly speeded up with its multi-pipeline. Besides it makes use of the continuity of image data to decrease the accesses to RAM This article uses Electronic System Level (ESL) tools to develop and simulate a cycle-accurate model of the cell array architecture. The result shows that cell array architecture with 200MHz clock can process 12 million HAAR features per second and detect faces on a 176*144 image at the frame rate of 103 frames per second, which is 14 times speedup compared with software implementation.
引用
收藏
页码：343 / 346
页数：4
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