共 50 条
- [1] The Hardware Implementation of a Novel Genetic Algorithm [J]. PROCEEDINGS OF WORLD ACADEMY OF SCIENCE, ENGINEERING AND TECHNOLOGY, VOL 8, 2005, 8 : 173 - 178
- [2] Hardware implementation of a novel genetic algorithm [J]. NEUROCOMPUTING, 2007, 71 (1-3) : 95 - 106
- [3] A novel image compression algorithm for hardware implementation [J]. PROCEEDINGS OF THE FOURTH IASTED INTERNATIONAL CONFERENCE ON CIRCUITS, SIGNALS, AND SYSTEMS, 2006, : 1 - +
- [4] A novel deadlock avoidance algorithm and its hardware implementation [J]. INTERNATIONAL CONFERENCE ON HARDWARE/SOFTWARE CODESIGN AND SYSTEM SYNTHESIS, 2004, : 200 - 205
- [6] Sorting Binary Numbers in Hardware - A Novel Algorithm and its Implementation [J]. ISCAS: 2009 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-5, 2009, : 2225 - 2228
- [9] THE FIRST HARDWARE MSC ALGORITHM IMPLEMENTATION [J]. NEURAL NETWORK WORLD, 2017, 27 (06) : 541 - 555
- [10] Hardware Implementation of ADABOOST ALGORITHM and Verification [J]. 2008 22ND INTERNATIONAL WORKSHOPS ON ADVANCED INFORMATION NETWORKING AND APPLICATIONS, VOLS 1-3, 2008, : 343 - 346