A Combined Analytical and Simulation-Based Model for Performance Evaluation of a Reconfigurable Instruction Set Processor

被引：0
|
作者：
Mehdipour, Farhad [1 ]
Noori, Hamid [2 ]
Javadi, Bahman [3 ]
Honda, Hiroaki [2 ]
Inoue, Koji [4 ]
Murakami, Kazuaki [4 ]
机构：
[1] Kyushu Univ, Fac Informat Sci & Elect Engn, Fukuoka 812, Japan
[2] Informat Technol & Nanotechnol, Inst Syst, Fukuoka, Japan
[3] Amirkabir Univ Technol, Comp Engn, Dept It, Tehran, Iran
[4] Kyushu Univ, Dept Informat, Fukuoka, Japan
来源：
PROCEEDINGS OF THE ASP-DAC 2009: ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE 2009 | 2009年
关键词：
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
Performance evaluation is a serious challenge in designing or optimizing reconfigurable instruction set processors. The conventional approaches based on synthesis and simulations are very time consuming and need a considerable design effort. A combined analytical and simulation-based model (CAnSO(*)) is proposed and validated for performance evaluation of a typical reconfigurable instruction set processor. The proposed model consists of an analytical core that incorporates statistics gathered from cycle-accurate simulation to make a reasonable evaluation and provide a valuable insight. Compared to cycle-accurate simulation results, CAnSO proves almost 2% variation in the speedup measurement.
引用
收藏
页码：564 / +
页数：2
相关论文
共 50 条
  • [1] Performance Evaluation of a Reconfigurable Instruction Set Processor
    Mehdipour, Farhad
    Noori, Hamid
    Honda, Hiroaki
    Inoue, Koji
    Murakami, Kazuaki
    [J]. ISOCC: 2008 INTERNATIONAL SOC DESIGN CONFERENCE, VOLS 1-3, 2008, : 184 - +
  • [2] Exploring opportunities to improve the performance of a reconfigurable instruction set processor
    Vassiliadis, N.
    Theodoridis, G.
    Nikolaidis, S.
    [J]. INTERNATIONAL JOURNAL OF ELECTRONICS, 2007, 94 (05) : 481 - 500
  • [3] The Design of Reconfigurable Instruction Set Processor Based on ARM Architecture
    Yin, Jinyong
    Xu, Zhenpeng
    Fang, Xinmo
    Zhou, Xihao
    [J]. ADVANCED COMPUTER ARCHITECTURE, 2018, 908 : 66 - 78
  • [4] Reconfigurable Instruction Set Processor Design Using Software Based Configuration
    Iqbal, M. Aqeel
    Awan, Uzma Saeed
    [J]. 2008 INTERNATIONAL CONFERENCE ON ADVANCED COMPUTER THEORY AND ENGINEERING, 2008, : 938 - 942
  • [5] A VLIW processor with reconfigurable instruction set for embedded applications
    Lodi, A
    Toma, M
    Campi, F
    Cappelli, A
    Canegallo, R
    Guerrieri, R
    [J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2003, 38 (11) : 1876 - 1886
  • [6] A VLIW processor with reconfigurable instruction set for embedded applications
    Campi, F
    Toma, M
    Lodi, A
    Cappelli, A
    Canegallo, R
    Guerrieri, R
    [J]. 2003 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE: DIGEST OF TECHNICAL PAPERS, 2003, 46 : 250 - +
  • [7] Intelligent Reconfigurable Instruction Set Processor (IRISP) design
    Aziz-Ur-Rehaman
    Syed, Aqeel A.
    Iqbal, M. Aqeel
    [J]. INMIC 2007: PROCEEDINGS OF THE 11TH IEEE INTERNATIONAL MULTITOPIC CONFERENCE, 2007, : 116 - 121
  • [8] Efficient processor instruction set extension by asynchronous reconfigurable datapath integration
    Becker, J
    Thomas, A
    Scheer, M
    [J]. 16TH SYMPOSIUM ON INTEGRATED CIRCUITS AND SYSTEMS DESIGN, SBCCI 2003, PROCEEDINGS, 2003, : 237 - 242
  • [9] A Platform for Multi Reconfigurable Instruction Set Processor System on Chip (MRPSoC)
    Soleymanpour, Rahim
    Mohammadi, Siamak
    [J]. 2013 17TH CSI INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE AND DIGITAL SYSTEMS (CADS 2013), 2013, : 99 - +
  • [10] Rapid Design Space Exploration of a Reconfigurable Instruction-Set Processor
    Mehdipour, Farhad
    Noori, Hamid
    Inoue, Koji
    Murakami, Kazuaki
    [J]. IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, 2009, E92A (12) : 3182 - 3192
12345