Intelligent Reconfigurable Instruction Set Processor (IRISP) design

Reconfigurable computing is being used to achieve high speed of Application Specific Integrated Circuits (ASICs), on the one hand, and the flexibility of the General Purpose Processors (GPPs), oil the other. However, due to the requirement of multiple reconfigurations to complete a computation, the recontiguration overhead might degrade the performance of the system. In order to avoid excessive reconfiguration, this paper presents all Intelligent Reconfigurable Instruction Set Processor (IRISP). The proposed processor is based oil an Intelligent Computational Analyzer Unit (ICAU), which intelligently analyzes and compares the newly required configuration with that of the existing configuration of the processor and makes it possible to reuse maximum of the existing resources, while reconfiguring only the required resources. It has been shown that the intelligent reutilization of the existing resources significantly improves the performance of the processor.