Performance Evaluation of a Reconfigurable Instruction Set Processor

被引：0
|
作者：
Mehdipour, Farhad [1 ]
Noori, Hamid [3 ]
Honda, Hiroaki [3 ]
Inoue, Koji [2 ]
Murakami, Kazuaki [2 ]
机构：
[1] Kyushu Univ, Res Inst Informat, Fukuoka 812, Japan
[2] Kyushu Univ, Dept Informat, Fukuoka 812, Japan
[3] Inst Syst, Informat Technol & Nanotechnol, Atsugi, Kanagawa, Japan
来源：
ISOCC: 2008 INTERNATIONAL SOC DESIGN CONFERENCE, VOLS 1-3 | 2008年
关键词：
Reconfigurable instruction set processors; analytical modeling; performance evaluation;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
Performance evaluation is a serious challenge in designing or optimizing reconfigurable instruction set processors. A combined analytical and simulation-based model (CAnSO*) is proposed and validated for performance evaluation of a typical reconfigurable instruction set processor. The proposed model consists of an analytical core that incorporates statistics gathered from cycle-accurate simulation to make a reasonable evaluation. CAnSO has clear speed advantages and compared to cycle-accurate simulation, it proves almost 2% variation in the speedup measurement.
引用
收藏
页码：184 / +
页数：2
相关论文
共 50 条
  • [1] Exploring opportunities to improve the performance of a reconfigurable instruction set processor
    Vassiliadis, N.
    Theodoridis, G.
    Nikolaidis, S.
    [J]. INTERNATIONAL JOURNAL OF ELECTRONICS, 2007, 94 (05) : 481 - 500
  • [2] A Combined Analytical and Simulation-Based Model for Performance Evaluation of a Reconfigurable Instruction Set Processor
    Mehdipour, Farhad
    Noori, Hamid
    Javadi, Bahman
    Honda, Hiroaki
    Inoue, Koji
    Murakami, Kazuaki
    [J]. PROCEEDINGS OF THE ASP-DAC 2009: ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE 2009, 2009, : 564 - +
  • [3] A VLIW processor with reconfigurable instruction set for embedded applications
    Lodi, A
    Toma, M
    Campi, F
    Cappelli, A
    Canegallo, R
    Guerrieri, R
    [J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2003, 38 (11) : 1876 - 1886
  • [4] A VLIW processor with reconfigurable instruction set for embedded applications
    Campi, F
    Toma, M
    Lodi, A
    Cappelli, A
    Canegallo, R
    Guerrieri, R
    [J]. 2003 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE: DIGEST OF TECHNICAL PAPERS, 2003, 46 : 250 - +
  • [5] Intelligent Reconfigurable Instruction Set Processor (IRISP) design
    Aziz-Ur-Rehaman
    Syed, Aqeel A.
    Iqbal, M. Aqeel
    [J]. INMIC 2007: PROCEEDINGS OF THE 11TH IEEE INTERNATIONAL MULTITOPIC CONFERENCE, 2007, : 116 - 121
  • [6] The Design of Reconfigurable Instruction Set Processor Based on ARM Architecture
    Yin, Jinyong
    Xu, Zhenpeng
    Fang, Xinmo
    Zhou, Xihao
    [J]. ADVANCED COMPUTER ARCHITECTURE, 2018, 908 : 66 - 78
  • [7] Efficient processor instruction set extension by asynchronous reconfigurable datapath integration
    Becker, J
    Thomas, A
    Scheer, M
    [J]. 16TH SYMPOSIUM ON INTEGRATED CIRCUITS AND SYSTEMS DESIGN, SBCCI 2003, PROCEEDINGS, 2003, : 237 - 242
  • [8] A Platform for Multi Reconfigurable Instruction Set Processor System on Chip (MRPSoC)
    Soleymanpour, Rahim
    Mohammadi, Siamak
    [J]. 2013 17TH CSI INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE AND DIGITAL SYSTEMS (CADS 2013), 2013, : 99 - +
  • [9] Rapid Design Space Exploration of a Reconfigurable Instruction-Set Processor
    Mehdipour, Farhad
    Noori, Hamid
    Inoue, Koji
    Murakami, Kazuaki
    [J]. IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, 2009, E92A (12) : 3182 - 3192
  • [10] Reconfigurable Instruction Set Processor Design Using Software Based Configuration
    Iqbal, M. Aqeel
    Awan, Uzma Saeed
    [J]. 2008 INTERNATIONAL CONFERENCE ON ADVANCED COMPUTER THEORY AND ENGINEERING, 2008, : 938 - 942
12345