Analyses of Single-Stage Complementary Self-Biased CMOS Differential Amplifiers

This paper analyzes and compares two complementary self-biased CMOS differential amplifiers. The two amplifiers differ only in terms of the number of output nodes, namely one is single-ended, the other being fully differential. Furthermore, the amplifiers are completely self-biased embedding the negative feedback in the biasing loop which makes them highly resistant to process, supply voltage and temperature variations. Both circuits are analyzed on the basis of small signals and expressions for gain are derived. The two amplifier topologies are simulated yielding a good match between the obtained results and the theory. Finally, discussed amplifiers featuring high gain and PVT immunity are well-suitable for implementation in nanometer CMOS processes.