A low-power soft error tolerant latch scheme

被引：0

作者：

Tajima, Saki ^{[1
]}

Shi, Youhua ^{[1
]}

Togawa, Nozomu ^{[1
]}

Yanagisawa, Masao ^{[1
]}

机构：

[1] Waseda Univ, Shinjuku Ku, Okubo 3-4-1, Tokyo 1698555, Japan

来源：

PROCEEDINGS OF 2015 IEEE 11TH INTERNATIONAL CONFERENCE ON ASIC (ASICON) | 2015年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

As process technology continues scaling, low power and reliability of integrated circuits are becoming more critical than ever before. Particularly, due to the reduction of node capacitance and operating voltage for low power consumption, it makes the circuits more sensitive to high-energy particles induced soft errors. In this paper, a soft-error tolerant latch called TSPC-SEH is proposed for soft error tolerance with low power consumption. The simulation results show that the proposed TSPC-SEH latch can achieve up to 42% power consumption reduction and 54% delay improvement compared to the existing soft error tolerant SEH and DICE designs.

引用

页数：4

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