High-speed area-efficient multiplier design using multiple-valued current-mode circuits - Comments

Kawahito et al present multiplier designs using the binary-tree reduction feature of certain highly redundant radix-2 representations, along with multiple-valued current-mode circuit techniques, and show them to compare favorably to those based on less redundant binary signed-digit and carry-save numbers. We point out that these representation schemes, and their potential advantages, have been discussed in earlier publications and that a more general view of the parallel-carries addition process exploited in these multipliers leads to other potentially useful representations.