High-speed area-efficient multiplier design using multiple-valued current-mode circuits - Reply

被引：0
|
作者：
Kawahito, S
Ishida, M
Nakamura, T
Kameyama, M
Higuchi, T
机构：
[1] TOYOHASHI UNIV TECHNOL,DEPT ELECT & ELECTR ENGN,TOYOHASHI,AICHI 441,JAPAN
[2] TOHOKU UNIV,GRAD SCH INFORMAT SCI,SENDAI,MIYAGI,JAPAN
来源：
IEEE TRANSACTIONS ON COMPUTERS | 1996年 / 45卷 / 05期
关键词：
D O I：
10.1109/TC.1996.509919
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
引用
收藏
页码：639 / 639
页数：1
相关论文
共 50 条
  • [1] HIGH-SPEED AREA-EFFICIENT MULTIPLIER DESIGN USING MULTIPLE-VALUED CURRENT-MODE CIRCUITS
    KAWAHITO, S
    ISHIDA, M
    NAKAMURA, T
    KAMEYAMA, M
    HIGUCHI, T
    [J]. IEEE TRANSACTIONS ON COMPUTERS, 1994, 43 (01) : 34 - 42
  • [2] High-speed area-efficient multiplier design using multiple-valued current-mode circuits - Comments
    Parhami, B
    [J]. IEEE TRANSACTIONS ON COMPUTERS, 1996, 45 (05) : 637 - 638
  • [3] High-speed parallel multiplier with redundant-code algorithm using multiple-valued MOS current-mode circuits
    He, CM
    Sun, YH
    [J]. 2001 4TH INTERNATIONAL CONFERENCE ON ASIC PROCEEDINGS, 2001, : 574 - 577
  • [4] A MULTIPLIER CHIP WITH MULTIPLE-VALUED BIDIRECTIONAL CURRENT-MODE LOGIC-CIRCUITS
    KAMEYAMA, M
    KAWAHITO, S
    HIGUCHI, T
    [J]. COMPUTER, 1988, 21 (04) : 43 - 56
  • [5] A Fault-Tolerant Area-Efficient Current-Mode ADC for Multiple-Valued Neural Networks
    Saffar, Farinoush
    Mirhassani, Mitra
    Ahmadi, Majid
    [J]. 2012 42ND IEEE INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC (ISMVL), 2012, : 250 - 255
  • [6] Design of High-Speed Quaternary D Flip-Flop Based on Multiple-valued Current-mode
    Wu, Haixia
    Bai, Yilong
    Li, Xiaoran
    Wang, Yiming
    [J]. 2020 4TH INTERNATIONAL CONFERENCE ON ELECTRICAL, AUTOMATION AND MECHANICAL ENGINEERING, 2020, 1626
  • [7] A 32X32-BIT MULTIPLIER USING MULTIPLE-VALUED MOS CURRENT-MODE CIRCUITS
    KAWAHITO, S
    KAMEYAMA, M
    HIGUCHI, T
    YAMADA, H
    [J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1988, 23 (01) : 124 - 132
  • [8] Design of an area-efficient CMOS multiple-valued current comparator circuit
    Kong, ZH
    Yeo, KS
    Chang, CH
    [J]. IEE PROCEEDINGS-CIRCUITS DEVICES AND SYSTEMS, 2005, 152 (02): : 151 - 158
  • [9] 32 multiplied by 32-BIT MULTIPLIER USING MULTIPLE-VALUED MOS CURRENT-MODE CIRCUITS.
    Kawahito, Shoji
    Kameyama, Michitaka
    Higuchi, Tatsuo
    Yamada, Haruyasu
    [J]. IEEE Journal of Solid-State Circuits, 1987, 23 (01)
  • [10] Reconfigurable current-mode multiple-valued residue arithmetic circuits
    Shimabukuro, K
    Zukeran, C
    [J]. 1998 28TH IEEE INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC - PROCEEDINGS, 1998, : 282 - 287
12345