High-speed area-efficient multiplier design using multiple-valued current-mode circuits - Reply

被引：0
|
作者：
Kawahito, S
Ishida, M
Nakamura, T
Kameyama, M
Higuchi, T
机构：
[1] TOYOHASHI UNIV TECHNOL,DEPT ELECT & ELECTR ENGN,TOYOHASHI,AICHI 441,JAPAN
[2] TOHOKU UNIV,GRAD SCH INFORMAT SCI,SENDAI,MIYAGI,JAPAN
来源：
IEEE TRANSACTIONS ON COMPUTERS | 1996年 / 45卷 / 05期
关键词：
D O I：
10.1109/TC.1996.509919
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
引用
收藏
页码：639 / 639
页数：1
相关论文
共 50 条
  • [41] A high-speed and area-efficient dual-rail PLA using divided and interdigitated column circuits
    Yamaoka, H
    Ikeda, M
    Asada, K
    [J]. IEICE TRANSACTIONS ON ELECTRONICS, 2004, E87C (06) : 1069 - 1077
  • [42] Design of current-mode CMOS multiple-valued schmitt triggers based on switch-signal theory
    Department of Information and Electronic Engineering, Zhejiang University, Hangzhou 310027, China
    [J]. Tien Tzu Hsueh Pao, 2006, 5 (924-927):
  • [43] Low-Power, High-Speed, and Area-Efficient Multiplier Based on the PTL Logic Style
    Pan, Wanyuan
    Yu, Yihe
    Tang, Chengcheng
    Yin, Ningyuan
    Yu, Zhiyi
    [J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2024, 71 (07) : 3538 - 3542
  • [44] DESIGN AND EVALUATION OF A CURRENT-MODE MULTIPLE-VALUED PLA BASED ON A RESONANT-TUNNELING TRANSISTOR MODEL
    DENG, X
    HANYU, T
    KAMEYAMA, M
    [J]. IEE PROCEEDINGS-CIRCUITS DEVICES AND SYSTEMS, 1994, 141 (06): : 445 - 450
  • [45] A self-restored current-mode CMOS multiple-valued logic design technique and its applications
    Teng, DHY
    Bolton, RJ
    [J]. 34TH INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC, PROCEEDINGS, 2004, : 204 - 209
  • [46] HIGH-SPEED CURRENT-MODE SENSE AMPLIFIER
    LAHIJI, GR
    SODAGAR, AM
    [J]. ELECTRONICS LETTERS, 1994, 30 (17) : 1371 - 1372
  • [47] An Area-Efficient CMOS Current-Mode Phase-Locked Loop
    DiClemente, D.
    Yuan, F.
    [J]. IEEE MWSCAS'06: PROCEEDINGS OF THE 2006 49TH MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL II, 2006, : 574 - +
  • [48] AN IMPLEMENTATION OF MULTIPLE-VALUED LOGIC AND FUZZY-LOGIC CIRCUITS USING 1.5 V BI-CMOS CURRENT-MODE CIRCUIT
    SASAKI, M
    TANIGUCHI, K
    OGATA, Y
    UENO, F
    INOUE, T
    [J]. IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, 1993, E76D (05) : 571 - 576
  • [49] Design and implementation of a low-power multiple-valued current-mode integrated circuit with current-source control
    Hanyu, T
    Kazama, S
    Kameyama, M
    [J]. IEICE TRANSACTIONS ON ELECTRONICS, 1997, E80C (07) : 941 - 947
  • [50] High-Speed and Area-Efficient Modified Binary Divider
    A. Azhagu Jaisudhan Pazhani
    T. S. Arun Samuel
    [J]. Circuits, Systems, and Signal Processing, 2022, 41 : 3350 - 3371
12345