Architecture of a stereo matching VLSI processor based on hierarchically parallel memory access

被引：0
|
作者：
Hariyama, M [1 ]
Sasaki, H [1 ]
Kameyama, M [1 ]
机构：
[1] Tohoku Univ, Grad Sch Informat Sci, Sendai, Miyagi 9808579, Japan
来源：
2004 47TH MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL II, CONFERENCE PROCEEDINGS | 2004年
关键词：
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
This paper presents a VLSI processor for highspeed and reliable stereo matching based on adaptive window-size control of SAD(Sum of Absolute Differences) computation. To reduce its computational complexity, SADs are computed using multi- resolution images. Parallel memory access is essential for highly parallel image processing. For parallel memory access, this paper also presents an optimal memory allocation that minimizes the hardware amount under the condition of parallel memory access at specified resolutions.
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页码：245 / 247
页数：3
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